AT45DB321D-CU datasheet(17/57 Pages) ATMEL

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3597N–DFLASH–04/09

AT45DB321D

9.1.3

Read Sector Protection Register Command

To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has

been asserted, an opcode of 32H and 3 dummy bytes must be clocked in via the SI pin. After the

last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the

SCK pins will result in data for the content of the Sector Protection Register being output on the

SO pin. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sector 1

and the last byte (byte 64) corresponds to sector 63. Once the last byte of the Sector Protection

output on the SO pin. The CS must be deasserted to terminate the Read Sector Protection Reg-

ister operation and put the output into a high-impedance state.

Note:

xx = Dummy Byte

Figure 9-4.

Read Sector Protection Register

9.1.4

Various Aspects About the Sector Protection Register

The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are

encouraged to carefully evaluate the number of times the Sector Protection Register will be

modified during the course of the applications’ life cycle. If the application requires that the Sec-

tor Protection Register be modified more than the specified limit of 10,000 cycles because the

application needs to temporarily unprotect individual sectors (sector protection remains enabled

while the Sector Protection Register is reprogrammed), then the application will need to limit this

practice. Instead, a combination of temporarily unprotecting individual sectors along with dis-

abling sector protection completely will need to be implemented by the application to ensure that

the limit of 10,000 cycles is not exceeded.

Command

Byte 1

Byte 2

Byte 3

Byte 4

Read Sector Protection Register

32H

xxH

Opcode

Data Byte

n + 1

Data Byte

n + 63

Each transition

represents 8 bits

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