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MAXQ3183-RAN+ 데이터시트(PDF) 79 Page - Maxim Integrated Products

부품명 MAXQ3183-RAN+
상세설명  Low-Power, Multifunction, Polyphase AFE with Harmonics and Tamper Detect
PDF  102 Pages
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제조업체  MAXIM [Maxim Integrated Products]
홈페이지  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAXQ3183-RAN+ 데이터시트(HTML) 79 Page - Maxim Integrated Products

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Low-Power, Multifunction, Polyphase AFE
with Harmonics and Tamper Detect
______________________________________________________________________________________
79
Number of Scan Frames per DSP Cycle (NS) (0x040)
The NS register defines the fundamental timing for the electricity meter. It defines a DSP cycle in terms the period of
the ADC scan frame. Generally, this register is calculated and updated automatically by the MAXQ3183 firmware
based on the zero-crossing detection, and whether noise rejection (REJ_NS) and averaging (AVG_NS) are enabled.
Host code can write to this register in order to set the desired DSP cycle duration. The duration of one scan frame
(tFR) is represented as 0x00010000.
Filter Coefficients
Line Cycle Noise Rejection Filter (REJ_NS) (0x02C)
This register establishes the sensitivity of the NS rejection filter setting. NS is a measure of the line frequency. If a line
cycle occurs that is shorter or longer than the line cycle represented in the NS register, this filter determines whether
the cycle is used to update the NS value. For more information, see the NS register description. If this register is
zero, noise rejection is disabled for the line cycle counter.
Bit:
15
14
13
12
11
10
9
8
Name:
Line Cycle Noise Rejection Filter High Byte
Reset:
0x00
Bit:
7
6
5
4
3
2
1
0
Name:
Line Cycle Noise Rejection Filter Low Byte
Reset:
0xC8
Bit:
31
30
29
28
27
26
25
24
Name:
Integer Portion, High Byte
Reset:
0x03
Bit:
23
22
21
20
19
18
17
16
Name:
Integer Portion, Low Byte
Reset:
0x28
Bit:
15
14
13
12
11
10
9
8
Name:
Fractional Portion, High Byte
Reset:
0x00
Bit:
7
6
5
4
3
2
1
0
Name:
Fractional Portion, Low Byte
Reset:
0x00



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