LSM320HAY30 datasheet(32/42 Pages) STMICROELECTRONICS

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LSM320HAY30

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Doc ID 16917 Rev 1

The BDU bit is used to inhibit output register updates between the reading of the upper and

lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are

updated continuously. If it is not certain to read faster than the output data rate, it is

recommended to set BDU bit to ‘1’. In this way, after the reading of the lower (upper) register

part, the content of that output register is not updated until the upper (lower) part is read

also. This feature avoids reading LSB and MSB related to different samples.

8.6

LA_CTRL_REG5 (24h)

TurnOn bits are used for turning on the sleep-to-wake function.

Table 28.

LA_CTRL_REG4 description

BDU

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated between MSB and LSB

reading)

BLE

Big/little endian data selection. Default value 0.

(0: data LSB @ lower address; 1: data MSB @ lower address)

FS1, FS0

Full-scale selection. Default value: 00.

(00: ±2

g; 01: ±4 g; 11: ±8 g)

STsign

Self-test sign. Default value: 00.

(0: self-test plus; 1 self-test minus)

Self-test enable. Default value: 0.

(0: self-test disabled; 1: self-test enabled)

SIM

SPI serial interface mode selection. Default value: 0.

(0: 4-wire interface; 1: 3-wire interface)

Table 29.

LA_CTRL_REG5 register

000

TurnOn1

TurnOn0

Table 30.

LA_CTRL_REG5 description

TurnOn1,

TurnOn0

Turn-on mode selection for sleep-to-wake function. Default value: 00.

Table 31.

Sleep-to-wake configuration

TurnOn1

TurnOn0

Sleep-to-wake status

Sleep-to-wake function is disabled

Turned on: The device is in low-power mode (ODR is defined in

LA_CTRL_REG1)

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