MPC5200B datasheet(32/72 Pages) FREESCALE

32 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

NOTES:

1 tUI, tMLI, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (sender or recipient) is waiting for

the other agent to respond with a signal before proceeding.

•tUI is an unlimited interlock that has no maximum time value.

•tMLI is a limited time-out that has a defined minimum.

•tLI is a limited time-out that has a defined maximum.

2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall

stop generating STROBE edges tRFS after negation of DMARDY. STROBE and DMARDY timing measurements are taken at

the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional

STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at

1.5 V.

t AZ

—

Maximum time allowed for output drivers to release

from being asserted or negated

A8.36

tZAH

—

Minimum delay time required for output drivers to

assert or negate from released state

A8.37

t ZAD

0—0—0—

A8.38

t ENV

Envelope time—from DMACK to STOP and

HDMARDY during data out burst initiation.

A8.39

t SR

—

STROBE to DMARDY time, if DMARDY is negated

before this long after STROBE edge, the recipient

receives no more than one additional data word.

A8.40

t RFS

—

Ready-to-Final STROBE time—no STROBE edges

are sent this long after negation of DMARDY.

A8.41

t RP

160

—

125

—

100

—

Ready-to-Pause time—the time recipient waits to

initiate pause after negating DMARDY.

A8.42

t IORDYZ

—

Pull-up time before allowing IORDY to be released.

A8.43

t ZIORDY

—

Minimum time drive waits before driving IORDY

A8.44

t ACK

—

Setup and hold times for DMACK, before assertion or

negation.

A8.45

t SS

—

Time from STROBE edge to negation of DMARQ or

assertion of STOP, when sender terminates a burst.

A8.46

Table 29. Ultra DMA Timing Specification (continued)

Sym

MODE 0

(ns)

MODE 1

(ns)

MODE 2

(ns)

Comment

SpecID

Min

Max

Min

Max

Min

Max

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