WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

8

INPUT VIDEO SAMPLING (INTERNAL VSMP)

MCLK

VSMP,

OUTPUT

VIDEO

SDO,

OUTPUT

t

PER

t

VSMPPD

t

VSMPPD

t

SDOPD

t

SDOPD

t

VSU

t

VH

t

RSU

t

RH

Figure 2 Input Video Timing (Internal VSMP)

TEST CONDITIONS

°C, MCLK = 48MHz unless

otherwise stated (AVDD denotes the voltage applied to all AVDD pins).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

20.8

ns

MCLK duty cycle

45

55

%

VSMP output propagation delay

15

25

ns

SDO output propagation delay

20

35

ns

Video level set-up time

10

ns

Video level hold time

10

ns

Reset level set-up time

10

ns

Reset level hold time

10

ns

Notes: 1.

2.

The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of

control bits RESREF[3:0].

3.

Parameters are measured at 50% of the rising/falling edge.