WM8148 datasheet(33/43 Pages) WOLFSON

33 / 43 page

WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

DEVICE CONFIGURATION

The following section details the Control Register Map, the contents of which determines the

operation of the WM8148, and the Control Bit table, which describes the possible settings of each of

the bits in the Control Register Map.

INTERNAL REGISTER DEFINITION

Table 6 details the internal register contents.

SET-UP REGISTER 1

• Selects global power on/off or selective enable.

• Selects the function of the SDO pin.

• Controls input sampling mode the device is operating in.

SET-UP REGISTER 2

• Enables individual sections of the device such as sample and hold blocks or PGA.

SET-UP REGISTER 3

• Sets the clamp and reset sample position in CDS modes.

• Sets the clamp position in non-CDS modes.

• Enables the internal clocks to be free running without VSMP.

• Allows the video and reset sample pulse widths to be reduced by half an MCLK period.

• Selects the channel that the sample is taken from in One-Channel (or line by line) modes.

SOFTWARE RESET

• Writing to this register causes the device to reset. Three different reset types are available.

See Control Bit Description Table for details.

SET-UP REGISTER 4

• Allows the latency through the device to be adjusted by ADC clock periods and by half-MCLK

periods.

• Enables VSMP as input or output.

• Allows the external setting of RLC bias reference voltage.

• Controls parallel/multiplexed output format.

• Defines the polarity of the output data.

COARSE OFFSETS

• Controls the non-CDS reference voltage level or reset clamp level.

• Allows external reference to be used as reset clamp level.

• Adjusts the d.c. level of the PGA outputs to align with the ADC input range to suit different input

video signal polarities.

REVISION NUMBER

• Allows the user to check which revision of the device is being used.

DAC VALUES

• Programmes the amount of offset applied to the input of each PGA. Table 7 describes the

sub-address bits for each channel.

PGA GAINS

• Programmes the gain of each PGA. Table 7 describes the sub-address bits for each channel.

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