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WM8170 데이터시트(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8170 데이터시트(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 41 page ![]() WM8170 Product Preview Rev 1.0 WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 30 STB D[9:2] DNA RNW ADDRESS DATA Z Z Figure25 Writing in Parallel Mode STB D[9:2] DNA RNW Z ADDRESS NORMAL OUTPUT DATA READ DATA Z Figure 26 Reading in Parallel Mode POWER DOWN CONTROL The WM8170 includes a separate power down pin, PDB. When this pin is taken low the whole device is powered down and all internal registers maintain their currently programmed value. Setting the PD0 bit in the Power Down 1 register can perform a similar power down operation. These two global power downs are logically OR’d. In addition to the above power down facilities the WM8170 contains seven other selective power downs of individual sections of the device. Setting the appropriate bit in the Power Down 2 register, as described in the Device Configuration section of this data sheet, will power down the particular part of the circuit. These bits are logically ANDed so that any combination of the available device sections can be powered down simultaneously |
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