WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

34

CONTROL BITS

DESCRIPTION

BLACK LEVEL TARGET (000100)

TARGET[7:0]

Target value for the black level.

PGA GAIN (000101)

GAIN[7:0]

Controls the PGA gain.

00hex is minimum gain

FFhex is maximum gain

DIGITAL DURATION (000110)

DIGDUR[3:0]

Digital correction duration: number of ADC conversion that are used to calculate the average.

DIGDUR3

DIGDUR2

DIGDUR1

DIGDUR0

Durations

0

0

0

0

1 ADC conversion

0

0

0

1

2 ADC conversions

0

0

1

0

4 ADC conversions

0

0

1

1

8 ADC conversions

0

1

0

0

16 ADC conversions

0

1

0

1

32 ADC conversions

0

1

1

0

64 ADC conversions

0

1

1

1

128 ADC conversions

1

0

0

0

256 ADC conversions

1

0

0

1

512 ADC conversions

1

0

1

0

1024 ADC conversions

1

0

1

1

2048 ADC conversions

1

1

0

0

2048 ADC conversions

1

1

0

1

2048 ADC conversions

1

1

1

0

2048 ADC conversions

1

1

1

1

2048 ADC conversions

ANALOGUE DURATION (000111)

ANDUR[6:0]

Controls the duration of the analogue loop enable - i.e. it represents the number of times that the up-down

counter will be clocked per falling edge of the BLCENB input.

THRESHOLD DETECT LSB / MSB (001001/10)

THRES[9:0]

Threshold detect value. If the corrected ADC output data is greater than the THRES[9:0] then PTDO will be

high. (Note PTDO[1:0] must be 00bin). Note THRES[9:0] is split into two registers, THRES[9:8] and

THRES[7:0].

POWER DOWN 1 (001011)

PDA

Global power down, OR'd with PDB pin

POWER DOWN 2 (001100)

PD[7:0]

Controls the analogue power downs. Note this is split over 2 registers (0 - block enabled, 1 - block powered

down).

PD0

S/H, PGA and the analogue correction loop power down

PD1

VMID and VCLP power down.

PD2

VRT and VRB power down.

PD3

ADC only power down.

PD4

AUX2DAC power down

PD5

AUX1DAC power down

AUXILIARY DAC 1

(001101)

AUX1DAC[7:0]

Auxiliary 1 DAC value

AUXILIARY DAC 2 (001110)

AUX2DAC[7:0]

Auxiliary 2 DAC value.