BD9102FVM, BD9104FVM, BD9106FVM

Technical Note

9/17

www.rohm.com

2009.05 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

●

Operation

BD9102FVM, BD9104FVM, BD9106FVM are the synchronous rectifying step-down switching regulator that achieves faster

transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width

Modulation) mode for heavier load, while it utilizes SLLM

efficiency.

○

Synchronous rectifier

It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,

and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power

dissipation of the set is reduced.

○

Current mode PWM control

Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.

・

PWM (Pulse Width Modulation) control

The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a

control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the

P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control

repeat this operation.

・

SLLM

When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse

is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without

voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.

Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current

Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is

tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the

switching dissipation and improves the efficiency.

Fig.44 Diagram of current mode PWM control

OSC

Level

Shift

Driver

Logic

RQ

S

SW

ITH

Current

Comp

Gm Amp.

SET

RESET

FB

Load

SENSE

Fig.45 PWM switching timing chart

Fig.46 SLLM

Current

Comp

SET

RESET

SW

PVCC

GND

GND

GND

SENSE

FB

Current

Comp

SET

RESET

SW

PVCC

GND

GND

GND

0A

SENSE

FB

Not switching