P89LPC970FDH datasheet(23/66 Pages) NXP

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P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

23 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.15.1 External interrupt inputs

The P89LPC970/971/972 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC970/971/972 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 7.17.3 “Power reduction modes” for details.

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