P89LPC970FDH datasheet(41/66 Pages) NXP

41 / 66 page

P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

41 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

7.28 Additional features

7.28.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

7.28.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects one of

the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS

bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1

7.29 Flash program memory

7.29.1 General description

The P89LPC970/971/972 flash memory provides in-circuit electrical erasure and

programming. The flash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase

operation will erase the entire program memory. ICP using standard commercial

programmers is available. In addition, IAP and byte-erase allows code memory to be used

for non-volatile data storage. On-chip erase and write timing generation contribute to a

user-friendly programming interface. The P89LPC970/971/972 flash reliably stores

memory contents even after 100000 erase and program cycles. The cell is designed to

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 15. Watchdog timer in Watchdog mode (WDTE = 1)

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aae542

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

400 kHz

oscillator

25 kHz

oscillator

crystal

oscillator

PCLK

XTALWD

(CLKCON.4)

WDMOD

(CLKCON.5)

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

reset(1)

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