MPC8308VMAFDA datasheet(26/88 Pages) FREESCALE

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

•

The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2.

•

SerDes reference clock receiver reference circuit structure

— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown

in Figure 16. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-

termination to XCOREVSS followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

•

The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock

driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the

exact common mode input voltage is not critical as long as it is within the range allowed by the

maximum average current of 8 mA (refer to the following bullet for more detail), since the

input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above XCOREVSS.

For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output

driven by its current source from 0mA to 16mA (0–0.8 V), such that each phase of the

differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage

at 400mV.

— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50

Ω to

XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be

AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

Figure 16. Receiver of SerDes Reference Clocks

Input

Amp

SD_REF_CLK

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