MPC5125 datasheet(41/92 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5125 Microcontroller Data Sheet, Rev. 3

Freescale Semiconductor

4.1.5

Power Dissipation

Power dissipation of the MPC5125 is caused by three different components:

•

Dissipation of the internal or core digital logic (supplied by VDD)

•

Dissipation of the analog circuitry (supplied by AVDD_SPLL and AVDD_CPLL)

•

Dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO)

Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the

dissipation due to the switching of the IO pins cannot be given in general, but must be calculated for each application case using

the following formula:

Eqn. 1

where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is

the switching frequency, and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the

MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded.

Eqn. 2

Table 10. Power Dissipation

Core Power Supply (VDD_core)

NOTES:

1 Typical core power is measured at V

DD_core = 1.4 V, TJ = 25 °C.

Mode

High-Performance

Unit

SpecID

e300 = 400 MHz, CSB = 200 MHz

Operational2

2 Operational power is measured while running an entirely cache-resident program with floating-point

multiplication instructions in parallel with DDR write operation.

620

D5.1

Doze3

580

D5.3

Nap3

235

D5.2

Sleep3

230

D5.4

Deep-sleep4

D5.5

RTC Power Supply (VBAT)

Hibernation

µW

D5.6

PLL/OSC Power Supplies (AVDD_SPLL, AVDD_CPLL, AVDD_OSC_TMPS)

Operational

D5.7

Deep-sleep

µW

D5.8

Unloaded I/O Power Supplies (VDD_IO, VDD_IO_MEM)

VDD_IO

VDD_IO_MEM

Operational

180

D5.9

Deep-sleep

D5.10

IOint

∑

CVDD_IO

total

core

analog

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