PIC24F04KA201 datasheet(56/224 Pages) MICROCHIP

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PIC24F04KA201 FAMILY

DS39937B-page 54

Preliminary

6.2

Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 6-3. Note that the system Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time at which the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

TABLE 6-3:

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

Reset Type

Clock Source

SYSRST Delay

System Clock

Delay

Notes

POR(6)

TPOR + TPWRT

—

1, 2

FRC, FRCDIV

TPOR + TPWRT

TFRC

1, 2, 3

LPRC

TPOR + TPWRT

TLPRC

1, 2, 3

ECPLL

TPOR + TPWRT

TLOCK

1, 2, 4

FRCPLL

TPOR + TPWRT

TFRC + TLOCK 1, 2, 3, 4

XT, HS, SOSC

TPOR+ TPWRT

TOST

1, 2, 5

XTPLL, HSPLL

TPOR + TPWRT

TOST + TLOCK

1, 2, 4, 5

BOR

TPWRT

—

FRC, FRCDIV

TPWRT

TFRC

2, 3

LPRC

TPWRT

TLPRC

2, 3

ECPLL

TPWRT

TLOCK

2, 4

FRCPLL

TPWRT

TFRC + TLOCK 2, 3, 4

XT, HS, SOSC

TPWRT

TOST

2, 5

XTPLL, HSPLL

TPWRT

TFRC + TLOCK 2, 3, 4

All Others

Any Clock

—

None

Note 1:

TPOR = Power-on Reset delay.

TPWRT = 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.

TFRC and TLPRC = RC Oscillator start-up times.

TLOCK = PLL lock time.

TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing

oscillator clock to the system.

If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC,

and in such cases, FRC start-up time is valid.

Note:

For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.

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