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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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16F648 데이터시트(PDF) 64 Page - Microchip Technology |
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16F648 데이터시트(HTML) 64 Page - Microchip Technology |
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64 / 180 page  PIC16F627A/628A/648A DS40044G-page 64 © 2009 Microchip Technology Inc. 10.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 10-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 17-2. FIGURE 10-1: COMPARATOR I/O OPERATING MODES Note 1: Comparator interrupts should be disabled during a Comparator mode change, otherwise a false interrupt may occur. 2: Comparators can have an inverted output. See Figure 10-1. C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Comparators Reset (POR Default Value) A A CM<2:0> = 000 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Two Independent Comparators A A CM<2:0> = 100 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Two Common Reference Comparators A D CM<2:0> = 011 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Off (Read as ‘0’) One Independent Comparator D D CM<2:0> = 101 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A C1 VIN- VIN+ Off (Read as ‘0’) Comparators Off D D CM<2:0> = 111 C2 VIN- VIN+ Off (Read as ‘0’) D D C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Four Inputs Multiplexed to Two Comparators A A CM<2:0> = 010 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A From VREF CIS = 0 CIS = 1 CIS = 0 CIS = 1 C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Two Common Reference Comparators with Outputs A D CM<2:0> = 110 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A Open Drain A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch. RA4/T0CKI/CMP2 C1 RA0/AN0 VIN- VIN+ RA3/AN3/CMP1 Three Inputs Multiplexed to Two Comparators A A CM<2:0> = 001 C2 RA1/AN1 VIN- VIN+ RA2/AN2/VREF A A CIS = 0 CIS = 1 VSS VSS RA0/AN0 RA3/AN3/CMP1 RA1/AN1 RA2/AN2/VREF Module C1VOUT C2VOUT C1VOUT C2VOUT Off (Read as ‘0’) Off (Read as ‘0’) C2VOUT C1VOUT C2VOUT C1VOUT C2VOUT C1VOUT C2VOUT |
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