ADT7476ARQZ-R7 datasheet(13/67 Pages) ONSEMI

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ADT7476

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2. The master initiates a read operation and sends the

alert response address (ARA = 0001 100). This is

a general call address that must not be used as a

specific device address.

3. The device whose SMBALERT output is low

responds to the alert response address, and the

master reads its device address. The address of this

device is now known and can be interrogated per

usual.

4. If more than one device’s SMBALERT output is

low, the one with the lowest device address has

priority in accordance with normal SMBus

arbitration.

5. Once the ADT7476 responds to the alert response

address, the master must read the status registers,

and SMBALERT is cleared only if the error

condition goes away.

SMBus Timeout

The ADT7476 includes an SMBus timeout feature. If

there is no SMBus activity for 35 ms, the ADT7476 assumes

the bus is locked and releases the bus. This prevents the

device from locking or holding the SMBus expecting data.

Some SMBus controllers cannot handle the SMBus timeout

feature, so if necessary, it can be disabled.

Configuration Register 1 (0x40)

[6] TODIS = 0, SMBus timeout enabled (default).

[6] TODIS = 1, SMBus timeout disabled.

Virus Protection

To prevent rogue programs or viruses from accessing

critical ADT7476 register settings, the lock bit can be set.

Setting Bit 1 of Configuration Register 1 (0x40) sets the lock

bit and locks critical registers. In this mode, certain registers

can no longer be written to until the ADT7476 is powered

down and powered up again. For more information on which

registers are locked see Table 14.

Voltage Measurement Input

The ADT7476 has four external voltage measurement

channels. It can also measure its own supply voltage, VCC.

Pin 20 to Pin 23 can measure 5.0 V, 12 V, and 2.5 V supplies,

and the processor core voltage VCCP (0 V to 3 V input). The

VCC supply voltage measurement is carried out through the

VCC pin (Pin 4). The 2.5 V input can be used to monitor a

chipset supply voltage in computer systems.

Analog−to−Digital Converter

All analog inputs are multiplexed into the on−chip,

successive−approximation, analog−to−digital converter,

which has a resolution of 10 bits. The basic input range is 0 V

to 2.25 V, but the inputs have built−in attenuators to allow

measurement of 2.5 V, 3.3 V, 5.0 V, 12 V, and the processor

core voltage VCCP without any external components. To

allow the tolerance of these supply voltages, the ADC

produces an output of 3/4 full scale (768 dec or 300 hex) for

the nominal input voltage, giving it adequate headroom to

cope with overvoltages.

Input Circuitry

The internal structure for the analog inputs is shown in

Figure 24 The input circuit consists of an input protection

diode, an attenuator, plus a capacitor to form a first−order

low−pass filter that gives input immunity to high frequency

noise.

Figure 24. Structure of Analog Inputs

VCCP

17.5kΩ

52.5kΩ

35pF

2.5VIN

45kΩ

94kΩ

30pF

VCC

68kΩ

71kΩ

30pF

5VIN

93kΩ

47kΩ

30pF

12VIN

120kΩ

20kΩ

30pF

MUX

Voltage Measurement Registers

Voltage Limit Registers

Associated with each voltage measurement channel is a

high and low limit register. Exceeding the programmed high

or low limit causes the appropriate status bit to be set.

Exceeding either limit can also generate SMBALERT

interrupts.

Table 5 shows the input ranges of the analog inputs and

output codes of the 10−bit ADC.

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