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STA015 데이터시트(PDF) 46 Page - STMicroelectronics |
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STA015 데이터시트(HTML) 46 Page - STMicroelectronics |
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46 / 56 page ![]() Obsolete Product(s) - Obsolete Product(s) STA015 46/56 6.3 TIMING DIAGRAMS 6.3.1 Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) Pad-timing versus load Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load. b) OCLK in input. Load (pF) Pad_timing 25 2.90ns 50 3.82ns 75 4.68ns 100 5.52ns OCLK (OUTPUT) SDO SCKT LRCLK tsdo tsckt tlrclk D98AU969 OCLK (INPUT) SDO SCKT LRCLK tsdo tsckt tlrclk D98AU970 thi tlo toclk |
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