MC68HC705MC4MP datasheet(85/180 Pages) FREESCALE

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16-Bit Timer

Output Compare

General Release Specification

16-Bit Timer

counter increments every four internal clock cycles. The minimum time

required to update the output compare registers is a function of software

rather than hardware.

The output compare output level bit (OLVL) will be clocked to its output

latch regardless of the state of the output compare flag bit (OCF). A valid

output compare must occur before the OLVL bit is clocked to its output

latch (TCMP).

NOTE:

The input capture 1 and the output compare functions share the same

data register and are, therefore, mutually exclusive. For example, the

output compare function is not available (including interrupts) when input

capture 1 is enabled.

Since neither the output compare flag (OCF) nor the output compare

registers are affected by reset, care must be exercised when initializing

the output compare function. The following procedure is recommended:

1. Block interrupts by setting the I bit in the condition code register

(CCR).

2. Write the MSB of the output compare register pair (OCRH) to

inhibit further compares until the LSB is written.

3. Read the timer status register (TSR) to arm the output compare

flag (OCF).

4. Write the LSB of the output compare register pair (OCRL) to

enable the output compare function and to clear its flag OCF (and

interrupt).

5. Unblock interrupts by clearing the I bit in the CCR.

This procedure prevents the output compare flag bit (OCF) from being

set between the time it is read and the time the output compare registers

are updated. A software example is shown in Figure 9-6.

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MC68HC705MC4MP 데이터시트(PDF) 85 Page - Freescale Semiconductor, Inc