전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

MC68HC705MC4MP 데이터시트(PDF) 93 Page - Freescale Semiconductor, Inc

부품명 MC68HC705MC4MP
상세설명  General Release Specification
PDF  180 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC68HC705MC4MP 데이터시트(HTML) 93 Page - Freescale Semiconductor, Inc

Back Button MC68HC705MC4MP Datasheet HTML 89Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 90Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 91Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 92Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 93Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 94Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 95Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 96Page - Freescale Semiconductor, Inc MC68HC705MC4MP Datasheet HTML 97Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 93 / 180 page
background image
16-Bit Timer
Timer Operation during Wait/Halt Modes
General Release Specification
16-Bit Timer
ICF1 — Input Capture 1 Flag
Bit 6 is set when the edge specified by IEDG1 in register TCR has
been sensed by the input capture edge detector fed by pin TCAP1.
This flag, and the input capture interrupt, can be cleared by reading
register TSR followed by reading the LSB of the input capture register
pair (ICRL1).
TOF — Timer Overflow Flag
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag, and the timer overflow interrupt, can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
OCF — Output Compare Flag
Bit 4 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag, and the output
compare interrupt, can be cleared by reading register TSR followed
by writing the LSB of the output compare register pair (OCRL).
9.8 Timer Operation during Wait/Halt Modes
During wait mode, the 16-bit timer continues to operate normally and
may generate an interrupt to trigger the MCU out of the wait mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com