MC68HC705MC4MP datasheet(89/180 Pages) FREESCALE

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16-Bit Timer

Input Capture

General Release Specification

16-Bit Timer

Reading the LSB of the input capture register pair (ICRL1, ICRL2) does

not inhibit transfer of the free-running counter. Again, minimum pulse

periods are ones that allow software to read the LSB of the register pair

(ICRL1, ICRL2) and perform needed operations. There is no conflict

between reading the LSB (ICRL1, ICRL2) and the free-running counter

transfer since they occur on opposite edges of the internal clock.

Figure 9-10. State Timing Diagram for Input Capture

INTERNAL

TIMER

T00

T01

T10

T11









INPUT CAPTURE

16-BIT

$FFEB

$FFED

$FFEE

$FFEC

NOTE:

INPUT CAPTURE

PREVIOUSLY CAPTURED VALUE

$FFED

INPUT CAPTURE

$FFEF

If the input capture edge occurs in the shaded area between T10 states, then the input capture

ﬂag becomes set during the next T11 state.

BUS CLOCK

CLOCKS

COUNTER

EDGE

LATCH

FLAG

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

MC68HC705MC4MP 데이터시트(PDF) 89 Page - Freescale Semiconductor, Inc

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