MC68HC705MC4MP datasheet(114/180 Pages) FREESCALE

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Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

Example 2

A write to PWMB-D ($12) will not invoke the data/control interlock.

However, if RA = RB, the write to either PWMB data register will

require a write to either PWMA data register to satisfy the channel

A/channel B interlock. Note that if a write was made to the PWMA

interlock data register, the channel A/channel B interlock would still be

satisfied but the data/control interlock will now be invoked for channel

A. A write to CTL-A control register is now necessary to satisfy the

channel A data/control interlock. Assuming UPDATE A and

UPDATE B are clear in the UPDATE register, the new contents of all

these registers will be transferred into their respective active registers

at the end of the current PWM cycle during which all invoked interlock

mechanisms become satisfied.

10.7.3 Operation with Different PWM Rates

If RA does not equal RB, channel A and channel B are assumed to be

operating independently of each other and are not interlocked. New data

values written to either PWM channel will occur as discussed in 10.7.1

Interlock Operation.

Interlocking between the channels only applies when both channels

have the same period (RA = RB). The RATE register is not interlocked

with any other registers but it is buffered. Changes to this register will

affect the PWM cycle subsequent to the write. Consequently, changing

the PWM period while generating a PWM signal will not cause erroneous

PWM operation (for example, glitches). Note that the RATE register is

treated as two separate 4-bit registers, each buffered with the

corresponding PWM channel cycle.

NOTE:

Changing the channels from having different periods to having the same

period may cause a phase difference between the channels due to

accumulated clock period difference. If synchronization is needed

between channel A and channel B, a PRESET cycle must be executed

to provide correct operation of the channel A/B interlock mechanism.

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MC68HC705MC4MP 데이터시트(PDF) 114 Page - Freescale Semiconductor, Inc