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MC68HC705MC4MP 데이터시트(PDF) 133 Page - Freescale Semiconductor, Inc

부품명 MC68HC705MC4MP
상세설명  General Release Specification
PDF  180 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC68HC705MC4MP 데이터시트(HTML) 133 Page - Freescale Semiconductor, Inc

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Serial Communications Interface
SCI I/O Registers
General Release Specification
Serial Communications Interface
11.6.4 SCI Status Register
The SCI status register contains flags to signal the following conditions:
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
TDRE — Transmit Data Register Empty
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set, and then writing to the SCDR.
Address:
$000D
Bit 7
654321
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
Write:
Reset:
1100000
U
= Unimplemented
U
= Unaffected
Figure 11-7. SCI Status Register (SCSR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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