PC912XDP512F0MPVR datasheet(406/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

406

Freescale Semiconductor

Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all

clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU

were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume

Table 9-6. IBCR Field Descriptions

Field

Description

IBEN

I-Bus Enable — This bit controls the software reset of the entire IIC bus module.

0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset

but registers can be accessed

1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect

If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode

ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected.

Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle

may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing

arbitration, after which bus operation would return to normal.

IBIE

I-Bus Interrupt Enable

0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt

condition

1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status

MS/SL

Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START

signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP

signal is generated and the operation mode changes from master to slave.A STOP signal should only be

generated if the IBIF ﬂag is set. MS/SL is cleared without generating a STOP signal when the master loses

arbitration.

0 Slave Mode

1 Master Mode

Tx/Rx

Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When

addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master

mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will

always be high.

0 Receive

1 Transmit

TXAK

Transmit Acknowledge Enable — This bit speciﬁes the value driven onto SDA during data acknowledge cycles

for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is

enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a

receiver, not a transmitter.

0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data

1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)

RSTA

Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the

current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus

is owned by another master, will result in loss of arbitration.

1 Generate repeat start cycle

RESERVED

Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0.

IBSWAI

I Bus Interface Stop in Wait Mode

0 IIC bus module clock operates normally

1 Halt IIC bus module clock generation in wait mode

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