PC912XDP512F0MPVR datasheet(410/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

410

Freescale Semiconductor

Figure 9-10. Start and Stop Conditions

9.4.1.2

Slave Address Transmission

The ﬁrst byte of data transfer immediately after the START signal is the slave address transmitted by the

master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired

direction of data transfer.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted by the master will respond by

sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 9-9).

No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an

address that is equal to its own slave address. The IIC bus cannot be master and slave at the same

time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate

correctly even if it is being addressed by another master.

9.4.1.3

Data Transfer

As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a

direction speciﬁed by the R/W bit sent by the calling master

All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address

information for the slave device.

Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while

SCL is high as shown in Figure 9-9. There is one clock pulse on SCL for each data bit, the MSB being

transferred ﬁrst. Each data byte has to be followed by an acknowledge bit, which is signalled from the

receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine

clock pulses.

If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The

master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to

commence a new calling.

SDA

SCL

START Condition

STOP Condition

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