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PC912XDP512F0MPVR 데이터시트(PDF) 409 Page - Freescale Semiconductor, Inc

부품명 PC912XDP512F0MPVR
상세설명  HCS12X Microcontrollers
PDF  1348 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 409 Page - Freescale Semiconductor, Inc

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
409
9.4
Functional Description
This section provides a complete functional description of the IICV2.
9.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure 9-9.
Figure 9-9. IIC-Bus Transmission Signals
9.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 9-9, a START
signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
SCL
SDA
Start
Signal
Ack
Bit
123
4567
8
MSB
LSB
123
4567
8
MSB
LSB
Stop
Signal
No
SCL
SDA
123
456
7
8
MSB
LSB
1
2
5
678
MSB
LSB
Repeated
34
99
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Calling Address
Read/
Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address
Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write



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