PC912XDP512F0MPVR datasheet(411/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

411

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end

of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.

9.4.1.4

STOP Signal

The master can terminate the communication by generating a STOP signal to free the bus. However, the

master may generate a START signal followed by a calling command without generating a STOP signal

ﬁrst. This is called repeated START. A STOP signal is deﬁned as a low-to-high transition of SDA while

SCL at logical 1 (see Figure 9-9).

The master can generate a STOP even if the slave has generated an acknowledge at which point the slave

must release the bus.

9.4.1.5

Repeated START Signal

As shown in Figure 9-9, a repeated START signal is a START signal generated without ﬁrst generating a

STOP signal to terminate the communication. This is used by the master to communicate with another

slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.

9.4.1.6

Arbitration Procedure

The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two

or more masters try to control the bus at the same time, a clock synchronization procedure determines the

bus clock, for which the low period is equal to the longest clock low period and the high is equal to the

shortest one among the masters. The relative priority of the contending masters is determined by a data

arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits

logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output.

In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a

status bit is set by hardware to indicate loss of arbitration.

9.4.1.7

Clock Synchronization

Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the

devices connected on the bus. The devices start counting their low period and as soon as a device's clock

has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to

high in this device clock may not change the state of the SCL line if another device clock is within its low

period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices

with shorter low periods enter a high wait state during this time (see Figure 9-10). When all devices

concerned have counted off their low period, the synchronized clock SCL line is released and pulled high.

There is then no difference between the device clocks and the state of the SCL line and all the devices start

counting their high periods.The ﬁrst device to complete its high period pulls the SCL line low again.

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