PC912XDP512F0MPVR datasheet(489/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

489

11.3.2.7

SCI Status Register 1 (SCISR1)

The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,

these registers can be polled by the MCU to check the status of these bits. The ﬂag-clearing procedures

require that the status register be read followed by a read or write to the SCI data register.It is permissible

to execute other instructions between the two steps as long as it does not compromise the handling of I/O,

but the order of operations is important for ﬂag clearing.

Read: Anytime

Write: Has no meaning or effect

76543210

TDRE

RDRF

IDLE

Reset

11000000

= Unimplemented or Reserved

Figure 11-10. SCI Status Register 1 (SCISR1)

Table 11-10. SCISR1 Field Descriptions

Field

Description

TDRE

Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the

SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value

to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data

0 No byte transferred to transmit shift register

1 Byte transferred to transmit shift register; transmit data register empty

Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break

character is loaded. TC is set high when the TDRE ﬂag is set and no data, preamble, or break character is being

transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1

(SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data,

preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of

the TC ﬂag (transmission not complete).

0 Transmission in progress

1 No transmission in progress

RDRF

Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI

data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data

0 Data not available in SCI data register

1 Received data available in SCI data register

IDLE

Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear

on the receiver input. Once the IDLE ﬂag is cleared, a valid frame must again set the RDRF ﬂag before an idle

condition can set the IDLE ﬂag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then

reading SCI data register low (SCIDRL).

0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared

1 Receiver input has become idle

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag.

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