PC912XDP512F0MPVR datasheet(490/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the

second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.

Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low

(SCIDRL).

0 No overrun

1 Overrun

Note: OR ﬂag may read back as set when RDRF ﬂag is clear. This may happen if the following sequence of

events occurs:

1. After the ﬁrst frame is received, read status register SCISR1 (returns RDRF set and OR ﬂag clear);

2. Receive second frame without reading the ﬁrst frame in the data register (the second frame is not

received and OR ﬂag is set);

3. Read data register SCIDRL (returns ﬁrst frame and clears RDRF ﬂag in the status register);

4. Read status register SCISR1 (returns RDRF clear and OR set).

Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy

SCIDRL read following event 4 will be required to clear the OR ﬂag if further frames are to be received.

Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as

the RDRF ﬂag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),

and then reading SCI data register low (SCIDRL).

0 No noise

1 Noise

Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle

as the RDRF ﬂag but does not get set in the case of an overrun. FE inhibits further data reception until it is

cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register

low (SCIDRL).

0 No framing error

1 Framing error

Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not

match the parity type bit (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the

case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low

(SCIDRL).

0 No parity error

1 Parity error

Table 11-10. SCISR1 Field Descriptions (continued)

Field

Description

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