PC912XDP512F0MPVR datasheet(496/1348 Pages) FREESCALE

496 / 1348 page

Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

496

Freescale Semiconductor

11.4.4

Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the

transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.

The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is

synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the

transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to one source of error:

•

Integer division of the bus clock may not give the exact target frequency.

Table 11-15 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.

When IREN = 0 then,

SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

1 The address bit identiﬁes the frame as an address

character. See Section 11.4.6.6, “Receiver Wakeup”.

Table 11-15. Baud Rates (Example: Bus Clock = 25 MHz)

Bits

SBR[12:0]

Receiver

Clock (Hz)

Transmitter

Clock (Hz)

Target

Baud Rate

Error

(%)

609,756.1

38,109.8

38,400

.76

308,642.0

19,290.1

19,200

.47

163

153,374.2

9585.9

9,600

.16

326

76,687.1

4792.9

4,800

.15

651

38,402.5

2400.2

2,400

.01

1302

19,201.2

1200.1

1,200

.01

2604

9600.6

600.0

600

.00

5208

4800.0

300.0

300

.00

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