PC912XDP512F0MPVR datasheet(499/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

499

When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic

1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal

goes low and the transmit signal goes idle.

If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register

continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE

to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1. Write the last byte of the ﬁrst message to SCIDRH/L.

2. Wait for the TDRE ﬂag to go high, indicating the transfer of the last frame to the transmit shift

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the ﬁrst byte of the second message to SCIDRH/L.

11.4.5.3

Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift

Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic

1, transmitter logic continuously loads break characters into the transmit shift register. After software

clears the SBK bit, the shift register ﬁnishes transmitting the last break character and then transmits at least

one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit

of the next frame.

The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received.

Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI

registers.

If the break detect feature is disabled (BKDFE = 0):

•

Sets the framing error flag, FE

•

Sets the receive data register full flag, RDRF

•

Clears the SCI data registers (SCIDRH/L)

•

May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF

(see 3.4.4 and 3.4.5 SCI Status Register 1 and 2)

If the break detect feature is enabled (BKDFE = 1) there are two scenarios1

The break is detected right from a start bit or is detected during a byte reception.

•

Sets the break detect interrupt flag, BLDIF

•

Does not change the data register full flag, RDRF or overrun flag OR

•

Does not change the framing error flag FE, parity error flag PE.

•

Does not clear the SCI data registers (SCIDRH/L)

•

May set noise flag NF, or receiver active flag RAF.

1. A Break character in this context are either 10 or 11 consecutive zero received bits

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