PC912XDP512F0MPVR datasheet(537/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

537

12.4.6

Error Conditions

The SPI has one error condition:

•

Mode fault error

12.4.6.1

Mode Fault Error

If the SS input becomes low while the SPI is conﬁgured as a master, it indicates a system error where more

than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not

permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the

MODFEN bit is set.

In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by

the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case

the SPI system is conﬁgured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur

in slave mode.

If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output

buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any

possibility of conﬂict with another output driver. A transmission in progress is aborted and the SPI is

forced into idle state.

If the mode fault error occurs in the bidirectional mode for a SPI system conﬁgured in master mode, output

enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in

the bidirectional mode for SPI system conﬁgured in slave mode.

The mode fault ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed

by a write to SPI control register 1. If the mode fault ﬂag is cleared, the SPI becomes a normal master or

slave again.

NOTE

If a mode fault error occurs and a received data byte is pending in the receive

shift register, this data byte will be lost.

12.4.7

Low Power Mode Options

12.4.7.1

SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a

low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are

disabled.

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