PC912XDP512F0MPVR datasheet(538/1348 Pages) FREESCALE

538 / 1348 page

Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

538

Freescale Semiconductor

12.4.7.2

SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.

•

If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode

•

If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation

state when the CPU is in wait mode.

–

If SPISWAI is set and the SPI is configured for master, any transmission and reception in

progress stops at wait mode entry. The transmission and reception resumes when the SPI exits

wait mode.

–

If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in

progress continues if the SCK continues to be driven from the master. This keeps the slave

synchronized to the master and the SCK.

If the master transmits several bytes while the slave is in wait mode, the slave will continue to

send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is

currently sending its SPIDR to the master, it will continue to send the same byte. Else if the

slave is currently sending the last received byte from the master, it will continue to send each

previous master byte).

NOTE

Care must be taken when expecting data from a master while the slave is in

wait or stop mode. Even though the shift register will continue to operate,

the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated

until exiting stop or wait mode). Also, the byte from the shift register will

not be copied into the SPIDR register until after the slave SPI has exited wait

or stop mode. In slave mode, a received byte pending in the receive shift

SPIDR copy is generated only if wait mode is entered or exited during a

tranmission. If the slave enters wait mode in idle mode and exits wait mode

in idle mode, neither a SPIF nor a SPIDR copy will occur.

12.4.7.3

SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held

high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the

transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is

exchanged correctly. In slave mode, the SPI will stay synchronized with the master.

The stop mode is not dependent on the SPISWAI bit.

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