PC912XDP512F0MPVR datasheet(539/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

539

12.4.7.4

Reset

The reset values of registers and signals are described in Section 12.3, “Memory Map and Register

Deﬁnition”, which details the registers and their bit ﬁelds.

•

If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit

garbage, or the byte last received from the master before the reset.

•

Reading from the SPIDR after reset will always read a byte of zeros.

12.4.7.5

Interrupts

The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is

a description of how the SPI makes a request and how the MCU should acknowledge that request. The

interrupt vector offset and interrupt priority are chip dependent.

The interrupt ﬂags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.

12.4.7.5.1

MODF

MODF occurs when the master detects an error on the SS pin. The master SPI must be conﬁgured for the

MODF feature (see Table 12-2). After MODF is set, the current transfer is aborted and the following bit is

changed:

•

MSTR = 0, The master bit in SPICR1 resets.

The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the

interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing

process which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”.

12.4.7.5.2

SPIF

SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does

not clear until it is serviced. SPIF has an automatic clearing process, which is described in

Section 12.3.2.4, “SPI Status Register (SPISR)”.

12.4.7.5.3

SPTEF

SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear

until it is serviced. SPTEF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI

Status Register (SPISR)”.

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