PC912XDP512F0MPVR datasheet(553/1348 Pages) FREESCALE

553 / 1348 page

Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

553

is set, an interrupt service is requested whenever the corresponding time-out ﬂag PTF in the PIT time-out

ﬂag (PITTF) register is set. The ﬂag can be cleared by writing a one to the ﬂag bit.

NOTE

Be careful when resetting the PITE, PINTE or PITCE bits in case of pending

PIT interrupt requests, to avoid spurious interrupt requests.

13.4.3

Hardware Trigger

The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel.

These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion

(please refer to the SoC Guide for the mapping of PITTRIG[3:0] signals to peripheral modules).

Whenever a timer channel time-out is reached, the corresponding PTF ﬂag is set and the corresponding

trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of

two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register

values PITLD = 0x0001 and PITMTLD = 0x0002 the ﬂag setting, trigger timing and a restart with force

load is shown in Figure 13-20.

13.5

Initialization/Application Information

13.5.1

Startup

Set the conﬁguration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the

conﬁguration registers can be written in arbitrary order.

13.5.2

Shutdown

When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are

cleared, the corresponding PIT interrupt ﬂags are cleared. In case of a pending PIT interrupt request, a

spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:

1. Reset the PIT interrupt ﬂags only in an ISR. When entering the ISR, the I mask bit in the CCR is

set automatically. The I mask bit must not be cleared before the PIT interrupt ﬂags are cleared.

2. After setting the I mask bit with the SEI instruction, the PIT interrupt ﬂags can be cleared. Then

clear the I mask bit with the CLI instruction to re-enable interrupts.

13.5.3

Flag Clearing

A ﬂag is cleared by writing a one to the ﬂag bit. Always use store or move instructions to write a one in

certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET

instructions. “BSET ﬂag_register, #mask” must not be used for ﬂag clearing because BSET is a

read-modify-write instruction which writes back the “bit-wise or” of the ﬂag_register and the mask into

the ﬂag_register. BSET would clear all ﬂag bits that were set, independent from the mask.

For example, to clear ﬂag bit 0 use: MOVB #$01,PITTF.

PC912XDP512F0MPVR 데이터시트(PDF) 553 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 553 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL