PC912XDP512F0MPVR datasheet(557/1348 Pages) FREESCALE

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Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

557

14.2

External Signal Description

Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply

voltages, most signals are power supply signals connected to pads.

Table 14-1 shows all signals of VREG_3V3 associated with pins.

NOTE

Check device level speciﬁcation for connectivity of the signals.

14.2.1

VDDR — Regulator Power Input Pins

Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads ﬂow through

this pin. A chip external decoupling capacitor (>=100 nF, X7R ceramic) between VDDR and VSSR (if VSSR

is not available VSS) can smooth ripple on VDDR.

For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.

14.2.2

VDDA, VSSA — Regulator Reference Supply Pins

Signals VDDA/VSSA, which are supposed to be relatively quiet, are used to supply the analog parts of the

regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling

capacitor (>=100 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this

supply.

14.2.3

VDD, VSS — Regulator Output1 (Core Logic) Pins

Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic.

These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).

In Shutdown Mode an external supply driving VDD/VSS can replace the voltage regulator.

Table 14-1. Signal Properties

Name

Function

Reset State

Pull Up

VDDR

Power input (positive supply)

—

VDDA

Quiet input (positive supply)

—

VSSA

Quiet input (ground)

—

VDD

Primary output (positive supply)

—

VSS

Primary output (ground)

—

VDDPLL

Secondary output (positive supply)

—

VSSPLL

Secondary output (ground)

—

VREGEN (optional)

Optional Regulator Enable

—

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