PC912XDP512F0MPVR datasheet(555/1348 Pages) FREESCALE

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MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

555

Chapter 14

Voltage Regulator (S12VREG3V3V5)

14.1

Introduction

Module VREG_3V3 is a dual output voltage regulator that provides two separate 2.5V (typical) supplies

differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3V up

to 5V (typical).

14.1.1

Features

Module VREG_3V3 includes these distinctive features:

•

Two parallel, linear voltage regulators

— Bandgap reference

•

Low-voltage detect (LVD) with low-voltage interrupt (LVI)

•

Power-on reset (POR)

•

Low-voltage reset (LVR)

•

Autonomous periodical interrupt (API)

14.1.2

Modes of Operation

There are three modes VREG_3V3 can operate in:

1. Full performance mode (FPM) (MCU is not in stop mode)

The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing

capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR

(power-on reset) are available. The API is available.

2. Reduced power mode (RPM) (MCU is in stop mode)

The purpose is to reduce power consumption of the device. The output voltage may degrade to a

lower value than in full performance mode, additionally the current sourcing capability is

substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. The API

is available.

3. Shutdown mode

Controlled by VREGEN (see device level speciﬁcation for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a

high-impedance state, only the POR feature is available, LVD and LVR are disabled. The API

internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the

VREG_3V3 to use external supplies.

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