PC912XDP512F0MPVR datasheet(564/1348 Pages) FREESCALE

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Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.21

564

Freescale Semiconductor

14.3.2.6

Reserved 06

The Reserved 06 is reserved for test purposes.

14.3.2.7

Reserved 07

The Reserved 07 is reserved for test purposes.

14.4

Functional Description

14.4.1

General

Module VREG_3V3 is a voltage regulator, as depicted in Figure 14-1. The regulator functional elements

are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on

reset module (POR), and a low-voltage reset module (LVR).

14.4.2

Regulator Core (REG)

Respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ

only in the amount of current that can be delivered.

The regulator is a linear regulator with a bandgap reference when operated in Full Performance Mode. It

acts as a voltage clamp in Reduced Power Mode. All load currents ﬂow from input VDDR to VSS or

VSSPLL. The reference circuits are supplied by VDDA and VSSA.

14.4.2.1

Full Performance Mode

In Full Performance Mode, the output voltage is compared with a reference voltage by an operational

ampliﬁer. The ampliﬁed input voltage difference drives the gate of an output transistor.

76543210

00000000

Reset

00000000

= Unimplemented or Reserved

Figure 14-8. Reserved 06

76543210

00000000

Reset

00000000

= Unimplemented or Reserved

Figure 14-9. Reserved 07

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