PC912XDP512F0MPVR datasheet(566/1348 Pages) FREESCALE

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Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.21

566

Freescale Semiconductor

The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency

is desired.

See Table 14-6 for the trimming effect of APITR.

NOTE

The ﬁrst period after enabling the counter by APIFE might be reduced.

The API internal RC oscillator clock is not available if VREG_3V3 is in

Shutdown Mode.

14.4.8

Resets

This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and

signals are provided in Section 14.3, “Memory Map and Register Deﬁnition”. Possible reset sources are

listed in Table 14-9.

14.4.9

Description of Reset Operation

14.4.9.1

Power-On Reset (POR)

During chip power-up the digital core may not work if its supply voltage VDD is below the POR

deassertion level (VPORD). Therefore, signal POR, which forces the other blocks of the device into reset,

is kept high until VDD exceeds VPORD. The MCU will run the start-up sequence after POR deassertion.

The power-on reset is active in all operation modes of VREG_3V3.

14.4.9.2

Low-Voltage Reset (LVR)

For details on low-voltage reset, see Section 14.4.5, “Low-Voltage Reset (LVR)”.

14.4.10 Interrupts

This section describes all interrupts originated by VREG_3V3.

The interrupt vectors requested by VREG_3V3 are listed in Table 14-10. Vector addresses and interrupt

priorities are deﬁned at MCU level.

Table 14-9. Reset Sources

Reset Source

Local Enable

Power-on reset

Always active

Low-voltage reset

Available only in Full Performance Mode

Table 14-10. Interrupt Vectors

Interrupt Source

Local Enable

Low-voltage interrupt (LVI)

LVIE = 1; available only in Full Performance

Mode

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