PC912XDP512F0MPVR datasheet(743/1348 Pages) FREESCALE

743 / 1348 page

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

745

Chapter 20

S12X Debug (S12XDBGV3) Module

20.1

Introduction

The S12XDBG module provides an on-chip trace buffer with ﬂexible triggering capability to allow

non-intrusive debug of application software. The S12XDBG module is optimized for the HCS12X 16-bit

architecture and allows debugging of both S12XCPU and XGATE module operations.

Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user

conﬁgures the S12XDBG module for a debugging session over the BDM interface. Once conﬁgured the

S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,

which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be conﬁgured

over a serial interface using SWI routines.

20.1.1

Glossary Of Terms

COF: Change Of Flow. Change in the program ﬂow due to a conditional branch, indexed jump or interrupt.

BDM : Background Debug Mode

DUG: Device User Guide, describing the features of the device into which the DBG is integrated.

WORD: 16 bit data entity

Data Line : 64 bit data entity

XGATE : S12X family programmable Direct Memory Access Module

CPU : S12X_CPU module

Tag : Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged

opcode reaches the execution stage a tag hit occurs.

20.1.2

Overview

The comparators monitor the bus activity of the S12XCPU and XGATE modules. When a match occurs

the control logic can trigger the state sequencer to a new state. On a transition to the Final State, bus tracing

is triggered and/or a breakpoint can be generated.

Independent of comparator matches a transition to Final State with associated tracing and breakpoint can

be triggered by the external TAGHI and TAGLO signals, by an XGATE module S/W breakpoint request

or an immediate trigger, instigated by writing to the TRIG control bit.

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