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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 745 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 745 Page - Freescale Semiconductor, Inc |
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745 / 1348 page  Chapter 20 S12X Debug (S12XDBGV3) Module MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 747 During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled. Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed. The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be generated if the MCU is secure. 20.1.5 Block Diagram Figure 20-1. Debug Module Block Diagram 20.2 External Signal Description The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation modes only. Table 20-1. Mode Dependent Restriction Summary BDM Enable BDM Active MCU Secure Comparator Matches Enabled Breakpoints Possible Tagging Possible Tracing Possible x x 1 Yes Yes Yes No 0 0 0 Yes Only SWI Yes Yes 0 1 0 Active BDM not possible when not enabled 1 0 0 Yes Yes Yes Yes 1 1 0 XGATE only XGATE only XGATE only XGATE only S12XCPU BUS TRACE BUFFER TRIGGER EXTERNAL TAGHI / TAGLO MATCH0 STATE XGATE BUS COMPARATOR B COMPARATOR C COMPARATOR D COMPARATOR A STATE SEQUENCER MATCH1 MATCH2 MATCH3 TRACE READ TRACE DATA (DBG READ DATA BUS) CONTROL SECURE BREAKPOINT REQUESTS XGATE S/W BREAKPOINT REQUEST TRIGGER TAG & TRIGGER CONTROL LOGIC TAGS TAGHITS STATE S12XCPU & XGATE |
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