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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

Table 20-3. DBGC1 Field Descriptions

Field

Description

ARM

Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by

user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with

tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the

S12XDBG module registers that can be written are ARM and TRIG.

0 Debugger disarmed

1 Debugger armed

TRIG

Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of

comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated

depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no

effect. If both TSOURCE bits are clear no tracing is carried out. If tracing has already commenced using BEGIN-

or MID trigger alignment, it continues until the end of the tracing session as deﬁned by the TALIGN bit settings,

thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect.

0 Do not trigger until the state sequencer enters the Final State.

1 Enter Final State immediately and issue forced breakpoint request when trace buffer is full.

XGSBPE

XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is

passed to the S12XCPU. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can

request an S12XCPU breakpoint depending on the state of this bit.

0 XGATE S/W breakpoint request is disabled

1 XGATE S/W breakpoint request is enabled

BDM

Background Debug Mode Enable — This bit determines if a S12X breakpoint causes the system to enter

Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). It has no affect on S12XDBG functionality.

If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI.

0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.

1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI

3–2

DBGBRK

S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint

to either S12XCPU or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the

breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is

generated immediately. Please refer to Section 20.4.7 for further details. XGATE software breakpoints are

independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the S12XCPU independent

of the DBGBRK bit ﬁeld conﬁguration. See Table 20-4.

1–0

COMRV

Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the

8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these

bits determine which register is visible at the address 0x0027. See Table 20-5.

Table 20-4. DBGBRK Encoding

DBGBRK

Resource Halted by Breakpoint

No breakpoint generated

XGATE breakpoint generated

S12XCPU breakpoint generated

Breakpoints generated for S12XCPU and XGATE

Table 20-5. COMRV Encoding

COMRV

Visible Comparator

Visible Register at 0x0027

Comparator A

DBGSCR1

Comparator B

DBGSCR2

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