PC912XDP512F0MPVR datasheet(772/1348 Pages) FREESCALE

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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

774

Freescale Semiconductor

20.4.4

State Sequence Control

Figure 20-23. State Sequencer Diagram

The state sequencer allows a deﬁned sequence of events to provide a trigger point for tracing of data in the

trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,

then state1 of the state sequencer is entered. Further transitions between the states are then controlled by

the state control registers and depend upon a selected trigger mode condition being met. From Final State

the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is

not restricted. Each transition updates the SSF[2:0] ﬂags in DBGSR accordingly to indicate the current

state.

Alternatively writing to the TRIG bit in DBGSC1, the Final State is entered and tracing starts immediately

if the TSOURCE bits are conﬁgured for tracing.

A tag hit through TAGHI/TAGLO brings the state sequencer immediately into state0, causes a breakpoint,

if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits

TALIGN[1:0].

Independent of the state sequencer, each comparator channel can be individually conﬁgured to generate an

immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.

Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer

transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a

channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This

is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state

sequencer enters state0 and the debug module is disarmed.

An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint

request to the S12XCPU immediately.

20.4.4.1

Final State

On entering Final State a trigger may be issued to the trace buffer according to the trace position control

as deﬁned by the TALIGN ﬁeld (see Section 20.3.2.3”). If the TSOURCE bits in the trace control register

DBGTCR are cleared then the trace buffer is disabled and the transition to Final State can only generate a

breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM

State1

Final State

State3

ARM = 1

Session Complete

(Disarm)

State2

State 0

(Disarmed)

ARM = 0

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