PC912XDP512F0MPVR datasheet(768/1348 Pages) FREESCALE

768 / 1348 page

Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

770

Freescale Semiconductor

before the tagged instruction executes (tagged-type trigger). Whilst tagging the RW, RWE, SZE, and SZ

bits are ignored and the comparator register must be loaded with the exact opcode address.

If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address

appears on the system address bus. If the selected address is an opcode address, the match is generated

when the opcode is fetched from the memory. This precedes the instruction execution by an indeﬁnite

number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address

when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an

opcode at odd address (n), the comparator register must contain address (n–1).

Once a successful comparator match has occurred, the condition that caused the original match is not

veriﬁed again on subsequent matches. Thus if a particular data value is veriﬁed at a given address, this

address may not still contain that data value when a subsequent match occurs.

Comparators C and D can also be used to select an address range to trace from. This is determined by the

TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 20-10. If the TRANGE

bits select a range deﬁnition using comparator D, then comparator D is conﬁgured for trace range

deﬁnition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range

deﬁnition using comparator C, then comparator C is conﬁgured for trace range deﬁnition and cannot be

used for address bus comparisons.

Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see

Section 20.3.2.4”). Comparator priority rules are described in the trigger priority section

(Section 20.4.3.6”).

20.4.2.1

Exact Address Comparator Match (Comparators A and C)

With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the

value stored in the comparator address/data registers. Further qualiﬁcation of the type of access (R/W,

word/byte) is possible.

Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact

address is compared, thus with the comparator address register loaded with address (n) a misaligned word

access of address (n–1) also accesses (n) but does not cause a match. Table 20-37 lists access

considerations without data bus compare. Table 20-36 lists access considerations with data bus

comparison. To compare byte accesses DBGXDH must be loaded with the data byte. The low byte must

be masked out using the DBGXDLM mask register. On word accesses the data byte of the lower address

is mapped to DBGXDH.

Table 20-36. Comparator A and C Data Bus Considerations

Access

Address

DBGxDH

DBGxDL

DBGxDHM

DBGxDLM

Example Valid Match

Word

ADDR[n]

Data[n]

Data[n+1]

$FF

MOVW #$WORD ADDR[n]

Byte

ADDR[n]

Data[n]

$FF

$00

MOVB #$BYTE ADDR[n]

Word

ADDR[n]

Data[n]

$FF

$00

MOVW #$WORD ADDR[n]

Word

ADDR[n]

Data[n+1]

$00

$FF

MOVW #$WORD ADDR[n]

PC912XDP512F0MPVR 데이터시트(PDF) 768 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 768 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL