PC912XDP512F0MPVR datasheet(793/1348 Pages) FREESCALE

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Chapter 21 External Bus Interface (S12XEBIV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

795

21.4.2

Internal Visibility

Internal visibility allows the observation of the internal MCU address and data bus as well as the

determination of the access source and the CPU pipe (queue) status through the external bus interface.

Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal

CPU and BDM accesses are made visible on the external bus interface, except those to BDM firmware and

BDM registers.

Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 21-9 to

Table 21-11), internal writes on ADDRx and DATAx (see Table 21-12 to Table 21-14). R/W and LSTRB

show the type of access. External read data are also visible on IVDx.

21.4.2.1

Access Source and Instruction Queue Status Signals

The access source (bus master) can be determined from the external bus control signals ACC[2:0] as

shown in Table 21-8.

The CPU instruction queue status (execution-start and data-movement information) is brought out as

IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.

21.4.2.2

Emulation Modes Timing

A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to

an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high

phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases.

Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and

(for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx

display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL

(0x0000) from the third until one cycle after the access to indicate continuation.

The resulting timing pattern of the external bus signals is outlined in the following tables for read, write

and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus

cycles. Non-shaded bold entries denote all values related to Access #0.

Table 21-8. Determining Access Source from Control Signals

ACC[2:0]

Access Description

000

Repetition of previous access cycle

001

CPU access

010

BDM access

011

XGATE PRR access1

1 Invalid IVD brought out in read cycles

100

No access2

2 Denotes also accesses to BDM ﬁrmware and BDM registers (IQSTATx are

‘XXXX’ and R/W = 1 in these cases)

101, 110, 111

Reserved

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