PC912XDP512F0MPVR datasheet(797/1348 Pages) FREESCALE

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Chapter 21 External Bus Interface (S12XEBIV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

799

Stretched accesses are controlled by:

1. EXSTR[2:0] bits in the EBICTL1 register conﬁguring ﬁxed amount of stretch cycles

2. Activation of the external wait feature by EWAITE in EBICTL1 register

3. Assertion of the external EWAIT signal when EWAITE = 1

The EXSTR[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles.

If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An arbitrary

amount of stretch cycles can be added using the EWAIT input.

EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle

for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional

cycles will cause the external bus access to be stretched accordingly.

Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed

and controlled by external wait after the data have been driven out on the external bus. This results in an

extension of time the bus signals and the related control signals are valid externally.

Read data are not captured by the system in normal expanded mode until the specified setup time before

the RE rising edge.

Read data are not captured in emulation expanded mode until the specified setup time before the falling

edge of ECLK.

In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by

EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is

not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched

as programmed and controlled by external wait.

21.4.5

Data Select and Data Direction Signals

The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of

the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses.

The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this

module exclusively supports these kind of accesses in a single cycle.

With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus

halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to

odd addresses.

In expanded modes the data access type is externally determined by a set of control signals, i.e., data select

and data direction signals, as described below. The data select signals are not available if using the external

bus interface with an 8-bit data bus.

21.4.5.1

Normal Expanded Mode

In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write),

data size and alignment of an external bus access (Table 21-17).

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