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PC912XDP512F0MPVR 데이터시트(PDF) 795 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 795 Page - Freescale Semiconductor, Inc |
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795 / 1348 page ![]() Chapter 21 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 797 21.4.2.2.2 Write Access Timing Table 21-12. Write Access (1 Cycle) Access #0 Access #1 Access #2 Bus cycle -> ... 123 ... ECLK phase ... high low high low high low ... ADDR[22:20] / ACC[2:0] ... addr 0 acc 0 addr 1 acc 1 addr 2 acc 2 ... ADDR[19:16] / IQSTAT[3:0] ... iqstat -1 iqstat 0 iqstat 1 ... ADDR[15:0] / IVD[15:0] ... ? x x ... DATA[15:0] (write) ... ? data 0 data 1 data 2 ... R/W ... 001111 ... Table 21-13. Write Access (2 Cycles) Access #0 Access #1 Bus cycle -> ... 123 ... ECLK phase ... high low high low high low ... ADDR[22:20] / ACC[2:0] ... addr 0 acc 0 addr 0 000 addr 1 acc 1 ... ADDR[19:16] / IQSTAT[3:0] ... iqstat-1 iqstat 0 0000 ... ADDR[15:0] / IVD[15:0] ... ? xx ... DATA[15:0] (write) ... ? data 0 x ... R/W ... 000011 ... Table 21-14. Write Access (n–1 Cycles) Access #0 Access #1 Bus cycle -> ... 123 ... n ... ECLK phase ... high low high low high low ... high low ... ADDR[22:20] / ACC[2:0] ... addr 0 acc 0 addr 0 000 addr 0 000 ... addr 1 acc 1 ... ADDR[19:16] / IQSTAT[3:0] ... iqstat-1 iqstat 0 0000 ... 0000 ... ADDR[15:0] / IVD[15:0] ... ? x x ... x ... DATA[15:0] (write) ... ? data 0 x ... R/W ... 000000 ... 11 ... |
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