PC912XDP512F0MPVR datasheet(877/1348 Pages) FREESCALE

877 / 1348 page

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

879

22.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the

port is used as input this bit is ignored.

22.3.2.71 Port AD1 Reduced Drive Register 1 (RDR1AD1)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each PAD[15:08] output pin as either full or reduced. If the

port is used as input this bit is ignored.

76543210

RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116

Reset

00000000

Figure 22-72. Port AD1 Reduced Drive Register 0 (RDR0AD1)

Table 22-63. RDR0AD1 Field Descriptions

Field

Description

7–0

RDR0AD1[23:16]

Reduced Drive Port AD1 Register 0

0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

76543210

RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110

RDR1AD19

RDR1AD18

Reset

00000000

Figure 22-73. Port AD1 Reduced Drive Register 1 (RDR1AD1)

Table 22-64. RDR1AD1 Field Descriptions

Field

Description

7–0

RDR1AD1[15:8]

Reduced Drive Port AD1 Register 1

0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

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