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PC912XDP512F0MPVR 데이터시트(PDF) 873 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 873 Page - Freescale Semiconductor, Inc |
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873 / 1348 page ![]() Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 875 22.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the port is used as input this bit is ignored. 22.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. 76543210 R RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 W Reset 00000000 Figure 22-66. Port AD0 Reduced Drive Register 1 (RDR1AD0) Table 22-59. RDR1AD0 Field Descriptions Field Description 7–0 RDR1AD0[7:0] Reduced Drive Port AD0 Register 1 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 76543210 R PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 W Reset 00000000 Figure 22-67. Port AD0 Pull Up Enable Register 1 (PER1AD0) Table 22-60. PER1AD0 Field Descriptions Field Description 7–0 PER1AD0[7:0] Pull Device Enable Port AD0 Register 1 0 Pull-up device is disabled. 1 Pull-up device is enabled. |
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