PC912XDP512F0MPVR datasheet(950/1348 Pages) FREESCALE

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

952

Freescale Semiconductor

23.0.5.54 Port J Data Register (PTJ)

Read: Anytime.

Write: Anytime.

Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0, the routed CAN0 modules and chip

select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not used with

any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

76543210

PTJ7

PTJ6

PTJ5

PTJ4

PTJ2

PTJ1

PTJ0

CAN4

TXCAN4

RXCAN4

SCI2

TXD2

RXD2

IIC0

SCL0

SDA0

Routed

CAN0

TXCAN0

RXCAN0

Alt.

Function

CS2

CS0

CS1

CS3

Reset

00000000

= Unimplemented or Reserved

Figure 23-56. Port J Data Register (PTJ)

Table 23-51. PTJ Field Descriptions

Field

Description

7–6

PJ[7:6]

The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general

purpose I/O function if the CAN4 module is enabled.

The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O

function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are conﬁgured

as open drain outputs. Refer to IIC section for details.

The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if

the routed CAN0 module is enabled. Refer to MSCAN section for details.

PJ2

The chip select function (CS1) takes precedence over the general purpose I/O.

PJ1

The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer

to SCI section for details.

PJ0

The chip select (CS3) takes precedence over the general purpose I/O function.

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