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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 998 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 998 Page - Freescale Semiconductor, Inc |
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998 / 1348 page  Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 1000 Freescale Semiconductor 24.0.5.12 Port K Data Direction Register (DDRK) Read: Anytime. Write: Anytime. This register controls the data direction for port K. DDRK determines whether each pin (except PK6) is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 24.0.5.13 Port T Data Register (PTT) Read: Anytime. Write: Anytime. Table 24-15. PORTK Field Descriptions Field Description 7–0 PK[7,5:0] Port K — Port K pins 7–0 can be used as general-purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read except for bit 6 which reads “0”. 76543210 R DDRK7 0 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 W Reset 00000000 Figure 24-14. Port K Data Direction Register (DDRK) Table 24-16. DDRK Field Descriptions Field Description 7–0 DDRK[7,5:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTK after changing the DDRK register. 76543210 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W ECT IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 Reset 00000000 Figure 24-15. Port T Data Register (PTT) |
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